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1、library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity trans38 is port( A:in std_logic_vector(2 downto 0); EN:in std_logic; Y:out std_logic_vector(7 downto 0) );end trans38;architecture dec_behave of trans38 is signal sel:std_logic_vector(3 downto 0);begin sel<=A&EN; with sel select Y<= "00000001" when "0001", "00000010" when "0011", "00000100" when "0101", "00001000" when "0111", "00010000" when "1001", "00100000" when "1011", "01000000" when "1101", "10000000" when "1111", "XXXXXXXX" when others;end dec_behave;。

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